The present invention relates to the field of semiconductor technology. Specifically, embodiments of the invention relate to semiconductor device structures and manufacturing methods.
The embedded silicon germanium (Embedded SiGe, or E-SiGe) process is widely used in advanced CMOS process technology to introduce compressive stress in the channel region, thus significantly improving the performance of PMOS. However, the inventor has observed that E-SiGe technology faces many challenges, including in unit processing (e.g., achieving high Ge content percentage, defect control, etc.) and integration issues (e.g., stress control, embedded SiGe shape, thermal compatibility, etc.).
In advanced CMOS processes, Σ type SiGe sources/drains are used to produce additional compressive stress to the channel in order to improve hole mobility. FIGS. 1A-1C illustrate a conventional process. FIG. 1A shows a substrate having an NMOS region and a PMOS region. A SiGe layer 101 is formed in the source/drain in the PMOS region. A Si cap layer 102 is formed on top of SiGe layer 101 to protect the layer of SiGe 101. As shown in FIG. 1B, dry etching is performed in the NMOS device regions to form spacer nitride (SiN) 103. Additionally, an ashing process is used to remove the photoresist in the PMOS region. These processes can cause loss of Si cap layer 102, which is exposed to plasma generated during dry etching and oxidation. During the subsequent process, Si cap layer 102 can suffer damages and losses such that SiGe layer 101 is not well protected, as shown in FIG. 1C.
Thus, an improved process for a SiGe source/drain is desired.